HM63021P-34(1/2)
il00d mode1 in
ck / rck in
res / rres in
di0 in
di1 in
di2 in
di3 in
di4 in
di5 in
di6 in
di7 in
we in
dec1 / wdec
/hi-z out
mode2 in
mode3 in
rdec / dec2 out
oe in
do0 out
do1 out
do2 out
do3 out
do4 out
do5 out
do6 out
do7 out
wres /ds in
dec3 out
wck / wt in
dec4 out gnd v cc 24
23
22
21
20
19
18
17
13 4
5
6
7
8
9
10
11
2
1
27
26
3
16
15 di0
di1
di2
di3
di4
di5
di6
di7
ck / rck
mode1
mode2
mode3/ rdec / dec2
res / rres
wres /ds/ dec3
wck / wt / dec4 do0
do1
do2
do3
do4
do5
do6
do7
dec1 / wdec 0 ; low level
1 ; high level
* ; dec output signal mode1 mode2 mode3 mode 1 1
1
0
0 1 1
0
1
0 1 0
* * * time base compressing
/expanding double speed exchange
tbc
1h/2h delay
delay line
mode1, 2, 3
rck wck ck rres res
di0 - di7
we
hi-z
wt
dec1, 2, 3, 4
wdec
rdec
ds
do0 - do7
oe ; mode select inputs
; read clock input
; write clock input
; clock input
; read reset input
; reset input
; data inputs
; write enable input
; high impedance
; write timing input
; decode pulse outputs
; write decode pulse output
; read decode pulse output
; delay select input
; data outputs
; output enable input we oe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 12 25 c-mos 16 k (2,048 x 8)-bit line memory ?op view
HM63021P-34(2/2) pin
no. 1
2
3
4 - 11
12
13
15
16
17 - 24
25
26
27 mode rck
rres
wck
wres hi-z
mode3 mode1
di0 - di7
we
do0 - do7
oe
mode2 ck
res
dec1
dec2 tbc
wdec
rdec wt
ds dec4
dec3 1h/2h
delay delay
line double
speed
exchange time base
compressing
/expanding read
address
control address
decoder output
buffer timing control
logic write
address
control write
row
decoder a (128 x 64)
memory matrix
b (128 x 64) we
latch address
decoder rdec
dec1
dec2
dec3
dec4 do0-do7 oe 25 wdec 13 mode3
mode2
mode1
wres/ds
wck/wt
rres/res
rck/ck 26 27 1 16 15 3 2 12 we di0 - di7 read
row
decoder read
column
decoder read
column
switch output
latch write
column
switch write
column
decoder input
latch input
buffer 26 13 26 15 16
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